普通触发器
library ieee;
use ieee.std_logic_1164.all;
entity dchu is
port (clk,d:in std_logic;
q:out std_logic);
end;
architecture ffq of dchu is
signal q1:std_logic;
begin process (clk,q1)
begin
if clk'event and clk='1'
then q1<=d; end if;
end process;
q<=q1; end ffq;